1. Field of the Invention
The present invention relates in general to a semiconductor device and method for fabricating the same. More particularly, it relates to a reduced-size split gate flash memory cell that increases integration with ICs.
2. Description of the Related Art
Non-volatile memory, such as flash memory, stores data regardless of electrical power supplied, and reads and writes data by controlling a threshold voltage of a control gate. Conventionally, flash memory includes a floating gate and a control gate. The floating gate stores charge and the control gate reads and writes data. Since flash memory has a high operating speed, it is widely applied for consumer electrical goods, such as digital cameras, mobile phones, personal stereos, and laptops.
FIGS. 1A–1F are cross-sections showing a conventional method of fabricating a split gate flash memory cell.
First, in FIG. 1A, a silicon substrate 10 is provided, and a thin silicon oxide layer 12 is formed thereon serving as a tunneling oxide layer. The tunneling oxide layer 12 can be formed by thermal oxidation. Next, a polysilicon layer 14 and a silicon nitride layer 16 are sequentially deposited on the tunneling oxide layer 12.
Next, in FIG. 1B, a photoresist layer 18 is coated on the silicon nitride layer 16, leaving a portion exposed. Thereafter, the exposed portion of the silicon nitride layer 16 is etched to form an opening 20 exposing the polysilicon layer 14.
Next, in FIG. 1C, the photoresist layer 18 is stripped and thermal oxidation is performed on the exposed polysilicon layer 14 using the remaining silicon nitride layer 16a as a mask to form a thick oxide layer 24 having tipped and thin portions 24a, 24b at its edge.
Next, in FIG. 1D, with the remaining silicon nitride layer 16a is removed by wet etching to expose the polysilicon layer 14.
Next, in FIG. 1E, the polysilicon layer 14 is etched by anisotrpic etching using thick oxide layer 24 as a mask to the tunneling oxide layer 12. The remaining polysilicon layer 14a is used as a floating gate.
Finally, in FIG. 1F, a gate dielectric layer 28, a control gate 30, and source region S/drain region D are formed and the tunneling oxide layer 12 uncovered by control gate 30 and the floating gate 14a is removed to finish the fabrication of the split gate flash memory cell.
However, in the fabrication of the conventional split gate flash memory, it is difficult to align the control gate and control the critical dimension (CD) of the control gate. Moreover, since increasing the integration of ICs is imperative, the conventional split gate flash memory is no longer suitable for small devices.